Board Coplanarity in SMT Project


Chair:  John Davignon (Intel Corporation)

Project objective:
Develop recommendations for measuring board land coplanarity during reflow to ensure high-quality, high-yield SMT process for the next generation of BGA components and boards. This new initiative will also work with IPC to create standards based on these recommendations.

Background:
The current specifications for component lead coplanarity and board bow and twist have not kept pace with developments in packaging and board technology. Some system manufacturers are experiencing poor SMT yields using materials that meet the current specifications.  The converse is also true. Some of the newest component technologies are hampered as they fail to meet the current component standards, but have demonstrated high yields in SMT.  It is clear that updated standards are needed that can provide the needed assurance of quality without impeding the continuous innovation that is basis of the industry.

New measurement techniques have enabled the measurement of flatness during simulated SMT conditions allowing more directly relevant standards to be developed.  Several standards bodies have already issued standards for using these techniques in components.  These efforts could be extended to ensure the flatness of system boards as well.

This iNEMI project will:
• Establish metrologies needed to measure board flatness in land area of components and connectors at both room and elevated temperatures.
• Develop strategy for setting requirements for differing board technologies and categories.
• Recommend acceptance criteria for board flatness and conditions for sampling and measurement requirements.

Implementing High Temperature Coplanarity Requirements for Components and PWBs (proposed) (PDF)

Statement of Work (Version 5.0, May 8, 2008)

Project Statement (Version 2.0, May 8, 2008) (Sign up ends on Friday, July 11, 2008)

Proposed project scope:

Phase I
1. Metrology development
    Key issues – Availability of applicable tools and outgoing monitors
    a. Literature survey of applicable methods
    b. Survey commercially available systems
    c. Round-robin testing of systems to understand limitations
    d. Draft best practices document for high temperature methods for board design validation
    e. Develop best practices for factory monitoring if required
2. Develop board flatness standards
    Develop a practical strategy for implementing new coplanarity standards for PWB.
    a. Select strategy for setting requirements for differing board technologies and categories
    b. Set acceptance criteria for board flatness
    c. Set conditions for sampling and measurement requirements

Phase II
Reconcile board and component requirements with JEDEC and JEITA.  Ensure that limitations of board manufacturing process are comprehended in all relevant standards.